MicroLib: Toward an Easier Quantitative Comparison of Micro-Architecture Mechanisms
Daniel Gracia Pérez, Gilles Mouchard, Olivier Temam
To appear at
Workshop on Duplicating, Deconstructing, and Debunking (WDDD04), Munich, Germany, June 19-20, 2004
Abstract
While most research papers include some performance
measurements, these performance numbers tend to be distrusted. Up to
the point that, after so many research articles on data cache
architectures, for instance, few researchers have a clear view of what
are the best data cache mechanisms. To illustrate the usefulness of a
fair comparison, we have picked a target architecture component for
which lots of optimizations have been proposed (data caches), and we
have implemented most of the hardware data cache optimizations
proposed in the past 4 years in top conferences. Then we have ranked
the different mechanisms, or more precisely, we have examined the
impact of benchmark selection, process model precision,... on
ranking, and obtained some surprising results. This study is part of a
broader effort, called MicroLib, aimed at promoting the
disclosure and sharing of simulator models.