Test And Reliability Team (T.A.R.T) is a research lab
in the Department of Electrical
and Computer Engineering of the University of
Wisconsin-Madison, USA. T.A.R.T is currently lead by
Prof. Kewal K.
Saluja and has five graduate students.
Our current research focus is on providing
various solutions for design for testability, built-in self-test,
reliable and testable computer architecture, and fault-tolerant computing.
The research in these areas involves fault
modeling, digital circuit design, test generation, design modification for
testability, built-in self-test and architectural simulations for fault
tolerance computing.
We are investigating techniques to make the test generation and fault
simulation process efficient for both combinational and sequential
circuits. For fault simulation, we are developing efficient algorithms for
cross-talk faults (both pulse and delay types) as well as conventional stuck-at faults.
In test generation and design for testability area, we are
investigating next generation DFT methods to solve emerging problems of
test application time, test power, and test data volum.
For the fault tolerant computing, a method for handling
operational-life faults in modern high performance processors will be
studied.
Refer to our research/project page
for details on recently completed work and on the
ongoing research and
projects.
