My general research interests
are test generation and testable and reliable design of digital systems.
In my research I make extensive use of VLSI CAD and analysis tools. The
research involves modeling of faults, designing digital circuits, test generation,
design modification for enhancing testability, and built-in self-testing
designs.
I am investigating techniques
to make the test generation and fault simulation process efficient for both
combinational and sequential circuits. In the area of built-in self-test,
my focus is on regular structures such as programmable logic arrays and
RAMs. I am developing algorithms and tools that can be used to synthesize
testable sequential circuits using partitioning and partial scan approach.
Much of my work is performed
using facilities of the VLSI digital system laboratory. The laboratory houses
a number of SUN stations, PCs, a small library of Journals, Conferences
and Proceedings.
