Journal Articles and Book Chapters

• Narrow Width Dynamic Scheduling [PDF]
  Erika Gunadi and Mikko H. Lipasti
  Journal of Instruction-Level Parallelism, Vol. 9, April 2007 (http://www.jilp.org/vol9).
• Circuit-Switched Coherence [IEEE Xplorer][PDF]
  Natalie Enright Jerger, Mikko Lipasti, and Li-Shiuan Peh
  IEEE Computer Architecture Letters, vol. 6, no. 1, Jan-Jun, 2007.
• Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays [IEEE Xplorer][PDF]
  Jason Cantin, Mikko H. Lipasti, James E. Smith, Andreas Moshovos, and Babak Falsafi
  IEEE Micro, Vol. 26, no. 1 (Special Issue on Top Picks in Computer Architecture), pp. 70-79.
• The Complexity of Verifying Memory Coherence and Consistency [IEEE Xplore][PDF]
  J. F. Cantin, M. H. Lipasti, and J. E. Smith
  IEEE Transactions on Parallel and Distributed Systems, Vol. 16, No. 7, July 2005.
• Memory ordering: a value-based Approach [IEEE Xplore] [PDF]
  Harold W. Cain and Mikko H. Lipasti
  IEEE Micro, vol.24, no.6, pp. 110- 117, Nov.-Dec. 2004 (Special Issue on Top Picks in Computer Architecture).
• Power Efficient Cache Coherence [PDF as published][PS as published]
  Full-length technical report version [PDF full-length][PS full-length]
  Craig Saldanha and Mikko H. Lipasti
  High Performance Memory Systems, edited by H. Hadimiouglu, D. Kaeli, J. Kuskin, A. Nanda, and J. Torrellas, Springer-Verlag, 2003.

• Dynamic Verification of Cache Coherence Protocols
  Jason F. Cantin, Mikko H. Lipasti, and James E. Smith
  High Performance Memory Systems, edited by H. Hadimiouglu, D. Kaeli, J. Kuskin, A. Nanda, and J. Torrellas, Springer-Verlag, 2003.

• Silent Stores and Store Value Locality[PDF][PS][.bib]
  Kevin M. Lepak, Gordon B. Bell, and Mikko H. Lipasti
  IEEE Transactions on Computers, Vol. 50, No. 11, November 2001

Conference Publications

• Virtual Tree Coherence: Leveraging Regions and In-Network Multicast Trees for Scalable Cache Coherence [PDF]
  Natalie Enright Jerger, Li-Shiuan Peh, and Mikko H. Lipasti
  To appear in Proceedings of the International Symposium on Microarchitecture (MICRO-41), Lake Como, Italy, November 2008.
• Skewed Redundancy [PDF]
  Gordon B. Bell and Mikko H. Lipasti
  To appear in Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT-17), October, 2008.
  
  
• An Accurate Flip-flop Selection Technique for Reducing Logic SER [PDF]
  Eric L. Hill, Mikko H. Lipasti, and Kewal K. Saluja
  Proceedings of The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-2008), Anchorage, Alaska, June 2008.
• Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support [PDF]
  Natalie Enright Jerger, Li-Shiuan Peh, and Mikko H. Lipasti
  In Proceedings of the International Symposium on Computer Architecture (ISCA-35), Beijing, China, June 2008.
• Circuit-Switched Coherence [PDF]
  Natalie Enright Jerger, Li-Shiuan Peh, and Mikko H. Lipasti
  In Proceedings of the IEEE Network on Chip Symposium, Newcastle-Upon-Tyne, UK, April 2008.
• Power-Aware DRAM Speculation [PDF]
  Nidhi Aggarwal, Jason Cantin, Mikko H. Lipasti, and James E. Smith
  in Proceedings of 14th International Symposium on High-Performance Computer Architecture (HPCA-14), Salt Lake City, UT, February 2008.
• Transparent Mode Flip-Flops for Collapsible Pipelines
  Eric Hill and Mikko H. Lipasti
  Proceedings of the 25th IEEE International Conference on Computer Design (ICCD-25), Lake Tahoe, CA, October 2007
• A Position-Insensitive Finished Store Buffer [PDF]
  Erika Gunadi and Mikko H. Lipasti
  In Proceedings of the 25th International Symposium on Computer Design (ICCD-25), Lake Tahoe, CA, October 2007. Slides available
• An Evaluation of Server Consolidation Workloads for Multi-core Designs [PDF]
  Natalie Enright Jerger, Dana Vantrease, and Mikko H. Lipasti
  In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), Boston, MA, September 2007.
• Power-Aware Operand Delivery [PDF]
  Erika Gunadi and Mikko H. Lipasti
  In Proceedings of International Symposium on Low Power Electronics and Design (ISLPED) , Portland, OR, August 2007. Poster available
• Speculative Optimization Using Hardware-Monitored Guarded Regions for Java Virtual Machines [PDF]
  Lixin Su and Mikko H. Lipasti
  In Proceedings of of the 3rd International ACM SIGPLAN/SIGOPS Conference on Virtual Execution Environments (VEE-3), San Diego, CA, June 2007.
• Stall Cycle Redistribution in a Transparent Fetch Pipeline [PDF]
  Eric Hill and Mikko H. Lipasti
  In Proceedings of Intl. Symposium on Low Power Electronics and Design, October 2006.
• Stealth Prefetching [PDF]
  Jason F. Cantin, Mikko H. Lipasti, and James E. Smith
  In Proceedings of: 12th Intl. Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XII), October 2006.
• Dynamic Class Hierarchy Mutation [PDF]
  Lixin Su and Mikko H. Lipasti
  In Proceedings of of the 4th International Symposium on Code Generation and Optimization (CGO-4), New York, NY, March 2006.
• Friendly Fire: Understanding the Effects of Multiprocessor Prefetching [PDF]
  Natalie Enright Jerger, Eric L Hill, and Mikko H. Lipasti
  In Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2006), Austin, TX, March 2006. Slides available
• An Approach for Implementing Efficient Superscalar CISC Processors [PDF]
  Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, and James E. Smith
  In Proceedings of of the 12th International Symposium on High-Performance Computer Architecture (HPCA-12), Austin, TX, February 2006.
• Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking [PDF]
  Jason F. Cantin, Mikko H. Lipasti, and James E. Smith
  In Proceedings of the 32nd International Symposium on Computer Architecture (ISCA-32), Madison, WI, June 2005.
• Reaping the Benefit of Temporal Silence to Improve Communication Performance [PDF]
  Kevin M. Lepak and Mikko H. Lipasti
  In Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2005), Austin, TX, March 2005.
• Memory Ordering: A Value-based Approach [PDF][PS][.bib]
  Harold W. Cain and Mikko H. Lipasti
  In Proceedings of the 31st International Symposium on Computer Architecture (ISCA-31), Munich, Germany, June 2004. Slides available
• Physical Register Inlining [PDF][PS]
  Mikko H. Lipasti, Brian R. Mestan, and Erika Gunadi
  In Proceedings of the 31st International Symposium on Computer Architecture (ISCA-31), Munich, Germany, June 2004. Slides available
• Deconstructing Commit [PDF][PS][.bib]
  Gordon B. Bell and Mikko H. Lipasti
  In Proceedings of the 4th International Symposium on Performance Analysis of Systems and Software (ISPASS-4), Austin, TX, March 2004. [Slides to be available]
• Understanding Scheduling Replay Schemes [PDF][PS][.bib]
  Ilhyun Kim and Mikko H. Lipasti
  In Proceedings of the 10th International Symposium on High-performance Computer Architecture (HPCA-10), Madrid, Spain, February 2004. [Slides to be available]
• Macro-op Scheduling: Relaxing Scheduling Loop Constraints [PDF][PS][.bib]
  Ilhyun Kim and Mikko H. Lipasti
  In Proceedings of the 36th International Symposium on Microarchitecture (MICRO-36), San Diego, CA, December 2003. Slides available
• Redeeming IPC as a Performance Metric for Multithreaded Programs [pdf, ps]
  Kevin M. Lepak, Harold W. Cain, and Mikko H. Lipasti
  In Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques, September, 2003.
  
  
• Constraint Graph Analysis of Multithreaded Programs [pdf, ps]
  Harold W. Cain, Mikko H. Lipasti, and Ravi Nair
  In Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques, September, 2003.
  
  
• Exploiting Partial Operand Knowledge [pdf, ps]
  Brian Mestan and Mikko H. Lipasti
  In Proceedings of the International Conference on Parallel Processing (ICPP-03), October, 2003.
  
  
• Half-Price Architecture [PDF][PS][.bib]
  Ilhyun Kim and Mikko H. Lipasti
  In Proceedings of the 30th International Symposium on Computer Architecture (ISCA-30), San Diego, CA, June 2003. Slides available pp
• A Case for Vector Network Processors [PDF]
  Madhusudanan Seshadri and Mikko H. Lipasti
  In Proceedings of: Network Processor Conference West, San Jose, CA, October 2002.
• Temporally Silent Stores [PDF][PS][.bib]
  Kevin M. Lepak and Mikko H. Lipasti
  In Proceedings of: 10th Intl. Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002. Slides available
• Verifying Sequential Consistency Using Vector Clocks [PDF][PS][.bib]
  Harold W. Cain and Mikko H. Lipasti
  In Proceedings of: 14th Symposium on Parallel Algorithms and Architectures Revue , August 2002. Slides to be available
• Avoiding Initialization Misses to the Heap [PDF][PS][.bib]
  Jarrod A. Lewis, Bryan Black, and Mikko H. Lipasti
  In Proceedings of: 29th International Symposium on Computer Architecture (ISCA-29), May 2002. Slides available
• Implementing Optimizations at Decode Time [PDF][PS][.bib]
  Ilhyun Kim and Mikko H. Lipasti
  In Proceedings of the 29th International Symposium on Computer Architecture (ISCA-29), May 2002. Slides available
• Correctly Implementing Value Prediction in Microprocessors that Support Multithreading or Multiprocessing [PDF][PS][.bib]
  Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, and Mikko H. Lipasti
  In Proceedings of:34th International Symposium on Microarchitecture, December 2001. Slides available
• An Architectural Evaluation of Java TPC-W [PDF][PS][.bib]
  Harold W. Cain, Ravi Rajwar, Morris Marden and Mikko H. Lipasti
  In proceedings of: The Seventh International Symposium on High-Performance Computer Architecture, January 2001. Slides available
• Silent Stores for Free [PDF][PS][.bib]
  Kevin M. Lepak and Mikko H. Lipasti
  In proceedings of: The 33rd Annual ACM/IEEE International Symposium on Microarchitecture (MICRO-33), December, 2000. Slides available
• Characterization of Silent Stores[PDF][PS][.bib]
  Gordon B. Bell, Kevin M. Lepak, and Mikko H. Lipasti
  International Conference on Parallel Architectures and Compilation Techniques, October, 2000. Slides available
• On the Value Locality of Store Instructions[PDF][PS][.bib]
  Kevin M. Lepak and Mikko H. Lipasti
  Proceedings of the 27th International Symposium on Computer Architecture, June, 2000. Slides available Trip pictures

Workshop Publications

• Achieving Fault Detection & Performance on CMPs [PDF]
  Gordon B. Bell and Mikko H. Lipasti
  SELSE 3 Workshop - Silicon Errors in Logic - System Effects, Austin, TX, March, 2007.
• Phase-based Adaptive Branch Predictor: Seeing the Forest for the Trees [PDF]
  Karthik Jayaraman, Vivek Shrivastava, Brian Pellin, Martin Hock, and Mikko H. Lipasti
  Workshop on Introspective Architecture, Austin, TX, February, 2006.
• Opportunities for Cache Friendly Process Scheduling [PDF]
  Pranay Koka and Mikko H. Lipasti
  Workshop on Interaction between Operating System and Computer Architecture, October, 2005. Slides available
• A Comparison of SPECjAppServer2002 and SPECjAppServer2004 [PDF]
  Lixin Su, Kingsum Chow, Kumar Shiv, and Ashish Jha
  Workshop on Computer Architecture Evaluation using Commercial Workloads, in conjunction with HPCA, February, 2005.
• Cache Pipelining with Partial Operand Knowledge [PDF]
  Erika Gunadi and Mikko H. Lipasti
  Workshop on Complexity-Effective Design, in conjunction with ISCA, June, 2004. Slides available
• Characterization of an IMAP Server on a Shared-Memory Multiprocessor [PDF] [PS]
  Pranay Koka and Mikko H. Lipasti
  Seventh Workshop on Computer Architecture Evaluation using Commercial Workloads , in conjunction with HPCA, February, 2004.
• Exploring Efficient SMT Branch Predictor Design [PDF] [PS]
  Matt Ramsay, Chris Feucht, and Mikko H. Lipasti
  Workshop on Complexity-Effective Design, in conjunction with ISCA, June, 2003.
• Precise and Accurate Processor Simulation [PDF] [PS]
  Harold W. Cain, Kevin M. Lepak, Brandon A. Schwartz, and Mikko H. Lipasti
  Workshop on Computer Architecture Evaluation using Commercial Workloads, in conjunction with HPCA, February, 2002.
• Comparison of Memory System Behavior in Java and Non-Java Commercial Workloads [PDF] [PS]
  Morris Marden, Shih-Lien Lu, Konrad Lai, and Mikko Lipasti
  Workshop on Computer Architecture Evaluation using Commercial Workloads, in conjunction with HPCA, February, 2002.
• Dynamic Verification of Cache Coherence Protocols [PDF] [PS]
  Jason F. Cantin, Mikko H. Lipasti, and James E. Smith
  Workshop on Memory Performance Issues, in conjunction with ISCA, June, 2001. Slides available
• Power Efficient Cache Coherence [PDF] [PS]
  Craig Saldanha and Mikko H. Lipasti
  Workshop on Memory Performance Issues, in conjunction with ISCA, June, 2001. Slides available
• A Dynamic Binary Translation Approach to Architectural Simulation [PDF] [PS]
  Harold W. Cain, Kevin M. Lepak and Mikko H. Lipasti
  Workshop on Binary Translation(WBT-2000), in conjunction with PACT, October, 2000. Slides available
Also appearing in Computer Architecture News, Vol. 29, No. 1, March 2001.

Theses and Technical Reports

• Latency- and Error-Tolerant Redundant Execution [PDF]
  Gordon B Bell, Ph.D. Thesis
  Submitted in partial fulfillment of the Ph.D. degree in ECE, December 2007
• Profligate Execution[PDF]
  Gordon B. Bell and Mikko H. Lipasti
  Technical Report, September 2006
• Dynamic Scheduling with Narrow Operand Values[PDF][PS]
  Erika Gunadi
  Submitted in partial fulfillment of the M.S. degree in ECE, June 2005
• Detecting and Exploiting Causal Relationships in Hardware Shared-Memory Multiprocessors [PDF]
  Harold W Cain
  Submitted in partial fulfillment of the Ph.D. degree in CS, Dec 2004
• Benefits of Value-Range Cache: A Limit Study [PDF][PS]
  Ramya K Narayana
  Submitted in partial fulfillment of the M.S. degree in ECE, May 2004
• Macro-op Scheduling and Execution [PDF]
  Ilhyun Kim, Ph.D. Thesis
  Submitted in partial fulfillment of the Ph.D. degree in ECE, May 2004
• Exploring, Defining, and Exploiting Recent Store Value Locality [PDF]
  Kevin M Lepak, Ph.D. Thesis
  Submitted in partial fulfillment of the Ph.D. degree in ECE, December 2003
• Dataflow Dominance: A Definition and Characterization [PDF][PS]
  Matt Ramsay
  Submitted in partial fulfillment of the M.S. degree in ECE, December 2003
• Exploiting Partial Operand Knowledge [PDF][PS]
  Brian Mestan
  Submitted in partial fulfillment of the M.S. degree in ECE, May, 2002
• Vector Network Processors [PDF][PS]
  Madhusudanan Seshadri
  Submitted in partial fulfillment of the M.S. degree in ECE, May, 2002
• Characterization of Silent Stores [PDF][PS]
  Gordon Bell
  Submitted in partial fulfillment of the M.S. degree in ECE, May 18, 2001
• A Genetic Algorithm for Designing Parallel Processor Interconnection Networks [PDF][PS]
  Morris Marden
  Submitted in partial fulfillment of the M.S. degree in ECE, May 18, 2001
• Performance and Power via Speculative Decode [PDF][PS]
  Ilhyun Kim
  Submitted in partial fulfillment of the M.S. degree in ECE, May 18, 2001
• Power Efficient Cache Coherence
  Craig Saldanha
  Submitted in partial fulfillment of the M.S. degree in ECE, May 18, 2001
• Silent Stores for Free: Reducing the Cost of Store Verification [PDF][PS]
  Kevin M. Lepak
  Submitted in partial fulfillment of the M.S. degree in ECE, December 15, 2000