As we move into the era of many-core processor chips, the area, power, and performance overheads of the on-chip interconnect becomes more and more important. We are actively investigating both electrical and optical networks along with co-designed cache coherence protocols for reducing these overheads in chips with sixteen or more cores per die.
Computer architects face broad new challenges in the twilight years of CMOS: while device density will continue to increase, device reliability, process variability, thermal, power delivery, and energy supply constraints will severely complicate any effort to extract additional performance and functionality from an abundant supply of on-chip transistors. This projects is focused on finding new ways to address these technology-related challenges by rethinking and restructuring conventional microarchitectural approaches to better suit the constraints of future CMOS technology.
Dynamic, managed run-time environments expose many previously- unavailable opportunities for optimizing machine code, especially in the presence of new program-model-induced constraints like strong exception models. This project attempts to find ways to exploit these opportunities by relying on hardware speculation support to relax correctness constraints and streamline both the optimization and the execution of applications.
The amazing computational abilities of the human neocortex are evident to everyone, yet their algorithmic underpinnings are surprisingly poorly understood by the scientific community. The two goals of this project are to (1) improve scientific understanding of cortical structures and algorithms, and (2) build future computing systems that employ similar, cortically-inspired mechanisms. We believe that such systems will be especially well-suited to future nanoscale technologies, since cortical algorithms are inherently tolerant of faults and variations.