I am a third year graudate student at UW-Madison, studying under Dr. Katherine Compton. I am currently researching reconfigurable computer architectures (see below). I recieved my MS degree in computer engineering at Lehigh University where I researched multithreaded database algorithms working under the guidance Dr. Henry F. Korth. I also recieved my BS in computer engineering at Lehigh University, and was (and am currently) an active member in the Lehigh Student ACM.
I am currently researching new techniques for coupling reconfigurable hardware with traditional general purpose microprocessors. My work is concentrating primarily on creating "safe" methods for allowing reconfigurable hardware to directly share the cache hierarchy with multiple processors cores that exist on a chip. To facilitate this work, I have developed a reconfigurable hardware simulator module for the GEMS/Simics full-system simulation platform. This simulator allows for both the development of reconfigurable applications, as well as the generation of "timing-accurate" runtimes on this platform.
My work has concentrated primarily in enabling the reconfigurable hardware to access its owner process's virtual memory. This is currently implemented in the simulator through the usage of a RH-specific TLB (translation lookaside buffer) as well as a Linux device driver that performs software page table lookups upon a request from the hardware. Upon a page miss the driver will issue a page table miss to the OS and stall the RH until the address translation is valid.
Currently I am examining the interconnection between the RH and main-memory. While our prior work allowed the RH to directly access the cache-hierarchy, it required that the RH implement address generation logic within it. We are currently examining the best way to automate this address generation logic, and studying the impact of multiple interacting hardware and software codes on the chip's cache performance.