Department of Electrical and Computer Engineering
University of Wisconsin - Madison
ECE 554 Digital Engineering Laboratory
COURSE CONDUCT
Spring 2007
1. OBJECTIVES:
1) Deal with problems and solutions associated with many aspects of a large digital design project,
2) Work effectively as a member of a moderate-sized team,
3) Use contemporary commercial design tools, and
4) Use programmable, user-defined devices for rapid prototyping.
2. PREREQUISITES: ECE 351, ECE/CS 552.

3. TEXTBOOK: Handouts, materials, and manuals on-line.

4. INSTRUCTORS:

Seapahn Megerian, 3423 EH, megerian@engr.wisc.edu
Office hours: TBD

Jake Adriaens: jtadriaens@wisc.edu
Office hours are assigned lab hours.

Ben Kopp: bjkopp@wisc.edu
Office hours are assigned lab hours.

4. LOCATIONS:

Laboratory: Room 3628 Engineering Hall (Phone in attached room 3654: 265-3803 - Campus Only)
Lectures: Room 3444 EH (W 12:05 PM)
Lectures, Design Reviews, and Group Meetings: Room 3444 EH (MW) and 3444 EH (TR) during lab hours, marked C on outline.

5. PROJECT: The project is to design, implement, test, and program a general or special purpose digital computer, usually emphasizing some particular features. Project groups are seven to nine in size. Teamwork and realistic project scheduling and monitoring are emphasized.

6. GRADING POLICY: 15% Lab Exercises; 20% Midterm/Bench Exam; 65% Project; No Final Exam.

7. TENTATIVE OUTLINE:

Week
 Date
Section
Topic or Activity
;nbsp;;nbsp;;nbsp;;nbsp;
1
1/24
 Lec Course Introduction
1/25
 Lab 1 C FPGA Concepts and Design
1/26
 Lab 2 C FPGA Concepts and Design
;nbsp;;nbsp;;nbsp;;nbsp;
2
1/29
 Lab 1 FPGA Design Tutorial, Miniproject Team Setups
1/30
 Lab 2 FPGA Design Tutorial, Miniproject Team Setups
1/31
 Lec Laboratory Environment, Miniproject Assignment
1/31
 Lab 1 Miniproject Organization and Design
2/1
 Lab 2 Miniproject Organization and Design
;nbsp;;nbsp;;nbsp;;nbsp;
3
2/5
 Lab 1 Miniproject Logic Design and Simulation
2/6
 Lab 2 Miniproject Logic Design and Simulation
2/7
 Lec Working in Teams
2/7
 Lab 1 Miniproject Synthesis and Debug
2/8
 Lab 2 Miniproject Synthesis and Debug
;nbsp;;nbsp;;nbsp;;nbsp;
4
2/12
 Lab 1 Miniproject Due, Course Project Team Setup
2/13
 Lab 2 Miniproject Due, Course Project Team Setup
2/14
 Lec Course Project Assignment
2/14
 Lab 1 Architecture Meeting
2/15
 Lab 2 Architecture Meeting
;nbsp;;nbsp;;nbsp;;nbsp;
5
2/19
 Lab 1 Architecture Meeting, Project Proposal Due
2/20
 Lab 2 Architecture Meeting, Project Proposal Due
2/21
 Lec --
2/21
 Lab 1 Architecture Meeting
2/22
 Lab 2 Architecture Meeting
;nbsp;;nbsp;;nbsp;;nbsp;
6
2/26
 Lab 1 Architecture Meeting
2/27
 Lab 2 Architecture Meeting
2/28
 Lec Register Files and Memory
2/28
 Lab 1 Architecture Review - 3444 EH
3/1
 Lab 2 Architecture Review - 3444 EH
;nbsp;;nbsp;;nbsp;;nbsp;
7
3/5
 Lab 1 Microarchitecture Meeting
3/6
 Lab 2 Microarchitecture Meeting
3/7
 Lec --
3/7
 Lab 1 Bench Exam, Microarchitecture Meeting
3/8
 Lab 2 Bench Exam, Microarchitecture Meeting
;nbsp;;nbsp;;nbsp;;nbsp;
8
3/12
 Lab 1 Microarchitecture Meeting
3/13
 Lab 2 Microarchitecture Meeting
3/14
 Lec --
3/14
 Lab 1 Logic Design & Entry
3/15
 Lab 2 Logic Design & Entry
;nbsp;;nbsp;;nbsp;;nbsp;
9
3/19
 Lab 1 Logic Design & Entry
3/20
 Lab 2 Logic Design & Entry
3/21
 Lec --
3/21
 Lab 1 Microarchitecture Review
3/22
 Lab 2 Microarchitecture Review
;nbsp;;nbsp;;nbsp;;nbsp;
10
3/26
 Lab 1 Logic Design & Simulation
3/27
 Lab 2 Logic Design & Simulation
3/28
 Lec --
3/28
 Lab 1 Subsystem Design & Simulation
3/29
 Lab 2 Subsystem Design & Simulation
;nbsp;;nbsp;;nbsp;;nbsp;
11
4/2 - 4/5
 Spring Break
;nbsp;;nbsp;;nbsp;;nbsp;
12
4/9
 Lab 1 System Design & Entry
4/10
 Lab 2 System Design & Entry
4/11
 Lec --
4/11
 Lab 1 System Simulation
4/12
 Lab 2 System Simulation
;nbsp;;nbsp;;nbsp;;nbsp;
13
4/16
 Lab 1 System Simulation & Debug
4/17
 Lab 2 System Simulation & Debug
4/18
 Lec --
4/18
 Lab 1 Hardware Test & Debug
4/19
 Lab 2 Hardware Test & Debug
;nbsp;;nbsp;;nbsp;;nbsp;
14
4/23
 Lab 1 Hardware Test & Debug
4/24
 Lab 2 Hardware Test & Debug
4/25
 Lec --
4/25
 Lab 1 Demo Preperation
4/26
 Lab 2 Demo Preperation
;nbsp;;nbsp;;nbsp;;nbsp;
15
4/30
 Lab 1 Software Test & Debug
5/1
 Lab 2 Software Test & Debug
5/2
 Lec Final Charge and Course Evaluation
5/2
 Lab 1 Project Completion
5/3
 Lab 2 Project Completion
;nbsp;;nbsp;;nbsp;;nbsp;
16
5/7
 Lab 1 Project Demonstration
5/8
 Lab 2 Project Demonstration
5/9
 Lec --
5/9
 Lab 1 (optional)
5/10
 Lab 2 (optional)
;nbsp;;nbsp;;nbsp;;nbsp;
17
5/16
 All
Final Project Report Due:
Wednesday 2:30 PM