Department of Electrical and Computer Engineering
University of Wisconsin - Madison
ECE 554 Digital Engineering Laboratory
COURSE CONDUCT
Fall 2003
1. OBJECTIVES:
To:
1) deal with problems and solutions associated
with many aspects of a large digital design project,
2) work effectively as a member of a moderate-sized team,
3) use contemporary commercial design tools, and
4) use programmable, user-defined devices for rapid prototyping.
2. PREREQUISITES: ECE
351, ECE/CS 552.
3. TEXTBOOK:
Handouts, materials, and manuals on-line.
4. INSTRUCTORS:
Please e-mail general technical questions to ece554@cae.wisc.edu.
Seapahn Megerian, 3423 EH, megerian@engr.wisc.edu
Office hours: TBD
Matt King: matthewking@wisc.edu
Office hours are assigned lab hours.
Arisandi Widsjaja: widjaja@cae.wisc.edu
Office hours are assigned lab hours.
4. LOCATIONS:
Laboratory: Room 3628 Engineering Hall (Phone in attached room 3654: 265-3803 - Campus Only)
Lectures: Room 2534 EH (W 12:05 PM)
Lectures, Design Reviews and Group Meetings: Room 2534 EH (During Lab Hours, marked C on outline).
5. PROJECT: The
project is to design, implement, test, and program a general or
special purpose digital computer, usually emphasizing some particular
features. Project groups are seven to nine in size. Teamwork and
realistic project scheduling and monitoring are emphasized.
6. GRADING POLICY:
15% Lab Exercises; 20% Midterm/Bench Exam; 65% Project; No Final
Exam.
7. TENTATIVE OUTLINE:
|
Week |
Date |
Section |
Topic or Activity |
|
1 |
9/3 |
Lec |
Course Introduction |
|
9/3 |
Lab 1 C |
FPGA Concepts and Design |
|
9/4 |
Lab 2 C |
FPGA Concepts and Design |
|
2 |
9/8 |
Lab 1 |
FPGA Design Tutorial, Lab Team Setups |
|
9/9 |
Lab 2 |
FPGA Design Tutorial, Lab Team Setups |
|
9/10 |
Lec |
Laboratory Environment, Project Assignment |
|
9/10 |
Lab 1 |
Miniproject - Organization |
|
9/11 |
Lab 2 |
Miniproject - Organization |
|
3 |
9/15 |
Lab 1 |
Miniproject - Logic Design and Entry |
|
9/16 |
Lab 2 |
Miniproject - Logic Design and Entry |
|
9/17 |
Lec |
Working in
Teams |
|
9/17 |
Lab 1 |
Miniproject - Simulation
|
|
9/18 |
Lab 2 |
Miniproject - Simulation |
|
4 |
9/22 |
Lab 1 |
Miniproject - Lab Work
|
|
9/23 |
Lab 2 |
Miniproject - Lab Work |
|
9/24 |
Lec |
Register Files and
Memory |
|
9/24 |
Lab 1 |
Catchup, Project - Architecture Meeting
|
|
9/25 |
Lab 2 |
Catchup, Project - Architecture Meeting |
| 5 |
9/29 |
Lab 1 |
Project - Architecture Meeting, PR 1
|
|
9/30 |
Lab 2 |
Project - Architecture Meeting, PR 1 |
|
10/1 |
Lec |
Team Scheduling |
|
10/1 |
Lab 1 |
Project - Architecture Meeting
|
|
10/2 |
Lab 2 |
Project - Architecture Meeting |
|
6 |
10/6 |
Lab 1 |
Project - Architecture Review
|
|
10/7 |
Lab 2 |
Project - Architecture Review |
|
10/8 |
Lec |
No Lecture |
|
10/8 |
Lab 1 |
Project - Microarchitecture Meeting
|
|
10/9 |
Lab 2 |
Project - Microarchitecture Meeting |
|
7 |
10/13 |
Lab 1 |
Project - Microarchitecture Meeting, PR 2 |
|
10/14 |
Lab 2 |
Project - Microarchitecture Meeting, PR 2 |
|
10/15 |
Lec |
No Lecture |
|
10/15 |
Lab 1 |
Midterm/Bench
Exam, Project - Microarchitecture Meeting |
|
10/16 |
Lab 2 |
Midterm/Bench
Exam, Project - Microarchitecture Meeting |
|
8
|
10/20 |
Lab 1 |
Project - Microarchitecture Meeting
|
|
10/21 |
Lab 2 |
Project - Microarchitecture Meeting
|
|
10/22 |
Lec |
No lecture |
|
10/22 |
Lab 1 |
Project - Microarchitecture Review
|
|
10/23 |
Lab 2 |
Project - Microarchitecture Review |
|
9
|
10/27 |
Lab 1 |
Project -
Logic Design & Entry |
|
10/28 |
Lab 2 |
Project -
Logic Design & Entry |
|
10/29 |
Lec |
No Lecture |
|
10/29 |
Lab 1 |
Project - Logic Design & Simulation
|
|
10/30 |
Lab 2 |
Project - Logic Design & Simulation |
|
10
|
11/3 |
Lab 1 |
Project -
Logic Design & Simulation |
|
11/4 |
Lab 2 |
Project -
Logic Design & Simulation |
|
11/5 |
Lec |
No Lecture |
|
11/5 |
Lab 1 |
Project - Subsystem Design & Simulation, PR 3 |
|
11/6 |
Lab 2 |
Project - Subsystem Design & Simulation, PR 3 |
|
11
|
11/10 |
Lab 1 |
Project - System Design & Entry |
|
11/11 |
Lab 2 |
Project - System Design & Entry |
|
11/12 |
Lec |
No Lecture |
|
11/12 |
Lab 1 |
Project -
System Simulation, PR 4 |
|
11/13 |
Lab 2 |
Project - System
Simulation, PR 4 |
|
12
|
11/17 |
Lab 1 |
Project -
System Simulation & Debug |
|
11/18 |
Lab 2 |
Project -
System Simulation & Debug |
|
11/19 |
Lec |
No Lecture |
|
11/19 |
Lab 1 |
Project - Hardware Test & Debug, PR 5 |
|
11/20 |
Lab 2 |
Project - Hardware Test & Debug, PR 5 |
|
13
|
11/24 |
Lab 1 |
Project -
Hardware Test & Debug |
|
11/25 |
Lab 2 |
Project -
Hardware Test & Debug |
|
11/26 |
Lec |
No Lecture |
|
11/26 |
Lab 1 |
Project - Demonstration Preparation |
|
11/27 |
Lab 2 |
Project - Demonstration Preparation (Thanksgiving break) |
|
14
|
12/1 |
Lab 1 |
Project - Software Test & Debug |
|
12/2 |
Lab 2 |
Project - Software Test & Debug |
|
12/3 |
Lec |
Final Charge and Course Evaluation |
|
12/3 |
Lab 1 |
Project - Software Completion, PR 6 |
|
12/4 |
Lab 2 |
Project - Software Completion, PR 6 |
|
15
|
12/8 |
Lab 1 |
Project
- Demonstration |
|
12/9 |
Lab 2 |
Project
- Demonstration |
|
12/10 |
Lec |
No Lecture |
|
12/10 |
Lab 1 |
Project - Feedback |
|
12/11 |
Lab 2 |
Project - Feedback |
|
16 |
12/17 |
All |
Final Project Report Due: Wednesday 2:30 PM |