Kevin Lepak's Homepage

Employer Information

I have recently finished my PhD ECE (Summer/Fall 2003), under Assistant Professor Mikko H. Lipasti at UW. My research interests while a graduate student included computer architecture and VLSI design/CAD. My thesis was on store value locality, aka, "silent stores". I am now working at Advanced Micro Devices in Austin, TX on high-performance computer architecture and performance modeling. You want to know something about K9? I know, but I can't tell you :-).

Research/Publications

The computer architecture research group I'm part of: The PHARM Team
I'm also affiliated with: VLSI Design and Design Automation Laboratory

Journal Publication:

Conference Publications:

Workshop Publications:

Other Publications:

Pictures and Stuff

Contact Information

You want to find me? Send me email: lepak@blackhole.ece.wisc.edu
If you are a human (and not a spambot) you will know to remove part of that email address before actually using it.

Microprocessor Design and Computer Architecture

My area of study in Electrical/Computer Engineering is high performance computer architecture. I was team leader and co-system architect for a microprocessor project in ECE554 Fall of 1998-1999 (so, quite a while ago now, as an undergraduate) that won the class design competition. Our system was pretty cool. Check out these if you're interested in information about our project for ECE554.

SMU2000, a Project in Computer Architecture

Project Description: SMU2000 is a 16 bit RISC architecture machine featuring a two-way superscalar pipelined (six stage) design. In addition, it is multithreaded with two hardware threads with the instruction mix between the threads determined dynamically at run time to maximize use of the two execution units. Primitives for synchronization are included in the system to allow implementation of shared memory semaphores, etc. SMU2000 uses a predicated instruction set to minimize branch penalties for short if/then/else code structures. SMU2000 also features complete predicate bypassing and partial (intra-alu) bypassing of data, making scheduling for the machine a bit more complicated to obtain maximum performance. SMU2000 is in-order and non-speculative.

For analysis of the performance effects of its various features, SMU2000 has the ability to enable or disable superscalar execution and each hardware thread, and also allows changing of the "priority" given to a thread in both hardware and software.

Here are some SMU2000 links:

Thanks for visiting!