FPGA 2008 Workshop

Designing with Extreme Parallelism

 Guy Lemieux
University of British Columbia
  Tarek El-Ghazawi
The George Washington University
 

Slides from the workshop are available as an entire set, and for individual parts of the workshop as listed below.

Modern FPGAs can implement large, custom compute engines that are designed to exploit extreme amounts of parallel computation. Through parallelism, these systems achieve orders of magnitude higher performance than the fastest microprocessors. Building such custom compute engines with existing hardware design languages is too difficult and time-consuming. For this to become mainstream technology, the task of designing such parallel systems must be as simple as possible. Thus, high-level languages are needed which can specify a custom compute engine or be compiled to run on predesigned parallel systems. In this workshop, we will examine several approaches for specifying extremely parallel computations in high-level languages. These can be used to build parallel systems in FPGAs, or they can be used to specify parallel computations in other competing architectures. By examining several different approaches, one gains insight into the best approach for solving a given problem. Ideally, this will also inspire new approaches for designing with extreme parallelism.

The workshop will start at 2pm on Sunday, Februrary 24th at the conference location.

 

 0.   Introductions
 
 1.   Overview
Prof. Tarek El-Ghazawi, The George Washington University
 
2. "Catapult C® Synthesis: Creating Parallel Hardware from C++"
Dr. Andres Takach, Chief Scientist, Mentor Graphics Corp.
 
3. "Hybrid CPU/FPGA Computing and Applications: Achieving Performance, Productivity, Portability"
Dr. Michael Babst, President, DSPlogic
 
4. "The Mitrion Virtual Processor: Using FPGAs in HPC"
Stefan Mohl, CTO, Mitrionics
 
5. "NVIDIA CUDA Software and GPU Parallel Computing Architecture"
Dr. David Kirk, Chief Scientist, NVIDIA

 

Categories and Subject Descriptors
B.6.1 [Logic Design]: Design Styles - Parallel circuits; D.1.3 [Programming Techniques]: Concurrent Programming - Parallel programming

General Terms
Algorithms, Design, Languages, Performance

Keywords
Custom compute engine, FPGA, hardware description language, high-level electronic design, parallel processing, reconfigurable computing

 

Copyright is held by the author/owner(s).
FPGA'08, February 24-26, 2008, Monterey, California, USA.
ACM 978-1-59593-934-0/08/02.