I am a PhD student in the ECE department, University
of Wisconsin-Madison, working with Assistant Professor Mikko H. Lipasti.
My research area is computer architecture, focusing on dynamic
instruction under scheduling loop constraints.
I am currently seeking an industrial position in microarchitecture
design or research, starting Summer 2004.
Resume (updated on Oct. 5, 2003) [PDF] [DOC]
[text]
Ilhyun Kim and Mikko H. Lipasti, Understanding Scheduling Replay Schemes,
To appear in proceedings of the 10th International Symposium on High
Performance Computer Architecture (HPCA-10), Madrid, Spain, February
2004. [PDF]
Ilhyun Kim and Mikko H. Lipasti, Macro-op Scheduling:
Relaxing Scheduling Loop Constraints, To appear in proceedings of
the 36th International Symposium on Microarchitecture (MICRO-36), San
Diego, CA, December 2003. [PDF]
Ilhyun Kim and Mikko H. Lipasti, Half-Price Architecture
, In proceedings of the 30th International Symposium on Computer
Architecture (ISCA-30), San Diego, CA, June 2003. [PDF]
Ilhyun Kim and Mikko H. Lipasti, Implementing
Optimizations at Decode Time, In proceedings of the 29th
International
Symposium on Computer Architecture (ISCA-29), Anchorage, AK, May
2002. [PDF]
Technical Reports:
Ilhyun Kim and Mikko H. Lipasti, Efficient Selective Recovery,
Feb. 2003.
Ilhyun Kim and Mikko H. Lipasti, Speculative decode: a
framework for runtime microarchitectural optimizations, June 2001.
Ilhyun Kim and Mikko H. Lipasti, Performance and Power via
Speculative Decode, November 2000. [PDF]
Ilhyun Kim and Mikko H. Lipasti, Group Verification of
Predicted Values, June 2000.
Stuff
My garbage directory. Do
you really want to see inside??
Oct 05, 2003: ikim rules. I am going to Spain!!
Aug 04, 2003: MOP paper got in.
May 28, 2003: Now, call me dissertator ikim. I've finished the
preliminary exam. Today is an important day in many aspects.
June 2003: Came back from ISCA in San Diego, CA.
Feb 2003: Working on Prelim document. I guess the title of the prelim
would be something like "Dynamic instruction execution under scheduling
latency constraints". What it implies is that I am going to study the
whole realm of speculative scheduling, optimization (performance /
hardware complexity), and recovery.
Jan 2003: The Half-price paper finally got in, which is a
really good news!! One step forward toward graduation.
March 2002: I am currently working on a complexity-effective
microarchitectural design. It will eventually eliminate the significant
amount of hardware complexity in the processor critical loop by doing
smart instruction scheduling, which I call Half-Price Architecture (funny
but I am serious).
